There is great interest in developing new working paradigms to complement and even replace current statically-wired computer architectures. One of the newest ideas is Chaos Computing which focuses on the development of devices with dynamic logic architecture and employs nonlinear or chaotic elements in logic operations. Application of chaos computing requires the development of dynamic logic gates (also called logic cells) that are able to change their response according to threshold reference signals and offset signals in order to produce different logic gates. These dynamic logic gates would support development of logic chips for next generation computers.
Current research that exploits the logic features of nonlinear dynamic systems through their electronic implementations, for example U.S. Pat. Nos. 8,091,062, 7,973,566, 7,924,059, 7,863,937, 7,415,683, 7,096,437, 7,453,285, 7,925,814, 7,925,131 and US patent application 2010/0219858, are related to chaotic computing architectures for logic gates based in nonlinear elements, while the present invention discloses dynamically configurable structures for linear core logic gates.
There are reports of computing modules that can be rewired to produce different outputs, but these devices employ static logic gates. For example, field programmable gate arrays (FPGAs) support rewiring and a limited degree of flexibility with respect to reconfiguration. Examples of modules that use static logic gates were presented in U.S. Pat. Nos. 6,025,735, 7,482,834, 5,748,009, 5,646,546 and Re. 35977. All are based on rewired static logic gates; different from the configurable structures for dynamic linear core logic gates presented in this application.
Reconfigurable computer modules based on chaotic or nonlinear elements (Chua's circuit or logistic map). Chua's circuit is easy to implement with off the shelf components. However, this device is not feasible to manufacture for integrated circuit technology because the required components (capacitors and inductor) occupy too much circuit area. The logistic map is based on a multiplier of its state, this produce the nonlinearity of the system and it is the core of the system. It should be noted that systems based on sensitive dependence on initial conditions are often very difficult to control in presence of noise because the nonlinear components.
In order to reduce the sensitive dependence on initial conditions of the nonlinear circuits and obtain a robust reconfigurable dynamic logic gate we have designed a method, circuit, array, and system to provide an implementation of a reconfigurable logic element using a linear core.